The present invention relates to an integrated circuit having capacitive elements for smoothing a supply voltage.
Integrated circuits are known in a multiplicity of embodiments and do not need to be explained in further detail. The smoothing of the supply voltage of integrated circuits by capacitors proves to be advantageous because the relevant integrated circuits can, as a result, operate in a manner free from interference and have a reduced electromagnetic emission. In this case, it is particularly advantageous, for reasons of area optimization in particular, if the capacitors which are provided for smoothing are likewise integrated in the integrated circuit. However, the capacitors provided in integrated circuits require a great deal of chip area in comparison with other integrated elements, which results in that the respective integrated circuit often becomes relatively large and hence also expensive, susceptible to faults and unwieldy.
Japanese Patent Application JP 2-250 370 A describes an integrated circuit in which the capacitors serving to smooth the supply voltage are disposed underneath the corresponding supply tracks via which the integrated circuit is supplied with the supply voltage. The capacitors are formed there by the interaction of poly sections, formed in a polysilicon layer of the integrated circuit, and the substrate regions lying underneath. All or some of the negative accompanying phenomena described above can be avoided in this way. In particular, the provision of capacitors provided for smoothing the supply voltage does not mean, or at any rate does not necessarily mean, that an integrated circuit that is constructed in such a way becomes larger than integrated circuits which do not contain such capacitors. However, to date the capacitors described in the Japanese Patent Application JP 2-250 370 A have, in many integrated circuits, not sufficed to smooth the supply voltage to the desired or required extent.
This is quite generally due to the fact that the so-called on-chip capacitances described above have a very large resistive component in their connection impedances, which results essentially from the high sheet resistances of the polysilicon or diffusion electrodes that are used in particular in the case of on-chip gate capacitances. This high resistive component in the connection impedances brings about a very low degree of attenuation at high frequencies, as a result of which high-frequency AC voltage components can be emitted into the system surrounding the integrated circuit, where such electromagnetic emissions can lead to interference with sensitive circuit elements.
It is accordingly an object of the invention to provide an integrated circuit having capacitive elements that overcomes the disadvantages of the prior art devices of this general type.
Taking the prior art as a departure point, the present invention is based on the object, therefore, of developing an integrated circuit of the generic type in such a way that the supply voltage of the circuit can be smoothed in the best possible way, in particular even in the case of high-frequency signals, without this being accompanied by an enlargement of the integrated circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit including a first supply track to be connected to a first supply potential and a second supply track to be connected to a second supply potential. The first supply potential and the second supply potential supply a supply voltage, and the first supply track and the second supply track form a first metallic layer. At least one second metallic layer having at least one third supply track to be connected to the first or second supply potential is provided. The second metallic layer is disposed in each case above the first metallic layer. At least one first capacitive element is disposed below the first metallic layer and the at least one third supply track and the first supply track and/or the second supply track define at least one second capacitive element. The first and second capacitive elements are provided for smoothing over the supply voltage.
The present invention makes it possible to provide, below the respective supply tracks, a maximum number of capacitors having an optimum efficiency. The total capacitance resulting from the parallel circuit of the respective capacitances is a maximum and can consequently smooth the supply voltage as optimally as possible, in particular even in the high-frequency range of the integrated circuit, without this being accompanied by an enlargement of the integrated circuit.
Since the regions below the supply tracks are typically not utilized at all in conventional integrated circuits, the integrated circuit, as a result of the integration of at least two capacitors which are connected in parallel with one another, does not become larger, or at most becomes minimally larger, than would be the case if there were no capacitor integration. The integrated circuit according to the invention can therefore be accommodated on a minimum area.
Furthermore, the proximity of the capacitors to the supply tracks which conduct the supply voltage to be smoothed makes it possible for the electrical connections which are required in order to dispose the capacitors effectively between the two poles of the supply voltage to be configured to be extremely short, as a result of which the integrated circuit is simple in its structure and in its production and is also reliable in operation.
In accordance with an added feature of the invention, the at least one first capacitive element is connected in parallel with the at least one second capacitive element.
In accordance with an additional feature of the invention, the at least one first capacitive element is one of a plurality of first capacitive elements disposed below both the first supply track and below the second supply track, and the at least one second capacitive element is one of a plurality of second capacitive elements.
In accordance with another feature of the invention, the second capacitive elements each have a capacitance and the first capacitive elements each have a capacitance at least a factor of 10 greater than the capacitance of the second capacitive elements.
In accordance with another added feature of the invention, a substrate having doping regions formed therein is provided along with a polysilicon layer having at least one poly section disposed above the substrate. The first capacitive elements are formed by an interaction of the poly section formed in the polysilicon layer and the doping regions formed in the substrate.
In accordance with another additional feature of the invention, an insulating material is disposed between the poly section and the first and second supply tracks. The insulating material has a plurality of plated-through holes formed therein connecting the first supply track of the first metal layer to the poly section.
In accordance with yet another feature of the invention, the second capacitive element is formed by an interaction of the third supply track and the first supply track.
In accordance with a further feature of the invention, the second capacitive element is formed by an interaction of the third supply track and the second supply track.
In accordance with a further added feature of the invention, the first capacitive elements and the second capacitive elements each have a capacitive component and a resistive component connected in series with the capacitive component. The resistive component of the second capacitive elements result from conductances of the first metallic layer and the at least one second metallic layer. The resistive component of the first capacitive elements result from conductances of the poly section and of corresponding ones of the doping regions in the substrate.
In accordance with a concomitant feature of the invention, the resistive component of the first capacitive elements is at least a factor of 10 greater than the resistive component of the second capacitive elements.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having capacitive elements, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.